library verilog;
use verilog.vl_types.all;
entity busint is
    port(
        iocs            : in     vl_logic;
        iorw            : in     vl_logic;
        rda             : in     vl_logic;
        tbr             : in     vl_logic;
        recbuf          : in     vl_logic_vector(7 downto 0);
        ioaddr          : in     vl_logic_vector(1 downto 0);
        \out\           : out    vl_logic_vector(7 downto 0);
        databus         : inout  vl_logic_vector(7 downto 0)
    );
end busint;
